Reverse HT on all AM2 chips?

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Devonavar
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Reverse HT on all AM2 chips?

Post by Devonavar » Sat Jun 24, 2006 11:20 am

This rumor has already been pointed out in this thread, but I think it deserves its own.

Summary: AMD has embedded a technology that allows dual core processors to appear as a single "virtual" processor into all AM2 chips.

The thread I linked to above cites the Inquirer as the original source, which puts its validity into a bit of question, but I found another, more reliable source.

This article on Xbitlabs is dated yesterday, before the story showed up on the Inquirer.

Also, The Tech Report has also posted a blurb about this.

With the Inquirer as the only source, I was inclinded to write this off as a rumour, but if Xbitlabs is the original source the story has a bit more creedence. Could this be real?

frostedflakes
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Post by frostedflakes » Sat Jun 24, 2006 12:28 pm

Really interesting stuff. I don't know if it will be enough, but it should give AMD a pretty good edge on Conroe... assuming it's all true, of course. :)

maukka
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Post by maukka » Sat Jun 24, 2006 1:42 pm

frostedflakes wrote:Really interesting stuff. I don't know if it will be enough, but it should give AMD a pretty good edge on Conroe... assuming it's all true, of course. :)
As it happens, it seems that Conroe also packs a similar feature:

http://www.xtremesystems.org/forums/sho ... p?t=104178

Woland
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Post by Woland » Sat Jun 24, 2006 4:58 pm

That Inquirer article is pretty funnny. They're always so dramatic, as if every next piece of technology is going to be the nail in the coffin for AMD or Intel (depending on who's holding the hammer at the time).

Anyway, just because you present two, three-issue cores as a single, six-issue core doesn't mean your threads' throughput all of a sudden doubles (sort of like adding an extra CPU doesn't make your computer twice as fast). The Inquirer is pretty disingenuous in trying to reduce this to a case of a six-issue "super K8" going against a four-issue Core 2. There's a reason CPU designers are moving to multicore chips--getting more ILP out of a thread isn't always possible, and therefore greater processor width isn't universally beneficial. There are workloads that maybe can make use of more issue slots per cycle, and there are workloads that can't even fully utilize the number they have available on a single K8 or NGMA core. Hell, a lot of people were skeptical of the advantage of increasing the issue-width to four (from three) when Intel introduced the NGMA.

Also, I think the tech they are talking about in Core 2 at the link, maukka, is something different: speculative thread execution (executing both branches--one on each core--and keeping the valid result after the branch is resolved). Then again, what we're talking around here with respect to AMD could be speculative threading, but it just got minintrepreted. Has AMD actually said anything about this?

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